1. Field of the Invention
Embodiments of the present invention generally relate to memory modules and, more specifically, to methods and apparatus for refresh management of memory modules.
2. Description of the Related Art
The storage capacity of memory systems is increasing rapidly due to various trends in computing, such as the introduction of 64-bit processors, multi-core processors, and advanced operating systems. Such memory systems may include one or more memory devices, such as, for example, dynamic random access memory (DRAM) devices. The cells of a typical DRAM device can retain data for a time period ranging from several seconds to tens of seconds, but to ensure that the data is properly retained and not lost, DRAM manufacturers usually specify a very low threshold for instituting a refresh operation. The specification for most modern memory systems containing DRAM devices is that the cells of the DRAM devices are refreshed once every 64 milliseconds. This means that each cell in a given DRAM device must be read out to the sense amplifier and then written back into the DRAM device at full signal strength once every 64 milliseconds. Furthermore, for some DRAM devices, to account for the effect of higher signal loss rate at higher temperature, the refresh rate is doubled when the device is operating above a standard temperature, typically above 85° C.
To simplify the task of ensuring that all DRAM cells are properly refreshed, most DRAM devices, including double data rate (DDR) and DDR2 synchronous DRAM (SDRAM) devices, have an internal refresh row address register that keeps track of the row identification (ID) of the last refreshed row. Typically, a memory controller sends a single refresh command to the DRAM device. Subsequently, the DRAM device increments the row ID in the refresh row address register and executes a sequence of standard steps (typically referred to a “row cycle”) to refresh the data contained in DRAM cells of all rows with the appropriate row ID's in all of the banks in the DRAM device.
With the advent of higher capacity DRAM devices, there are more cells to refresh. Thus, to properly refresh all DRAM cells in a higher capacity DRAM device, either the refresh operations need to be performed more frequently or more cells need to be refreshed with each refresh command. To simplify memory controller design, the choice made by DRAM device manufacturers and memory controller designers is to keep the frequency of refresh operations the same, but refresh more DRAM cells for each refresh operation for the higher capacity DRAM devices. However, one issue associated with the action of refreshing more DRAM devices for each refresh operation in the higher capacity DRAM devices is that larger electrical currents may be drawn by the higher capacity DRAM devices for each refresh operation.
As the foregoing illustrates, what is needed in the art are new techniques for refreshing multiple memory devices in a memory system. In particular, higher capacity DRAM devices that must refresh a large number of DRAM cells for each refresh command.